Electronic Design

Examining the RISC-V Architecture

RISC-V is an open-source instruction set definition managed by RISC-V International. This TechXchange includes content that delves into the architecture and design of a RISC-V processor core. How did ...
EDN

RISC-V basics: The truth about custom extensions

The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), ...
redsharknews.com

The key CPU architecture you've never heard of: RISC-V

The RISC-V CPU architecture currently accounts for under 1% of the world’s processor market, but that is going to change rapidly over the next years as its parallel processing is perfectly suited to ...
Geeky Gadgets

RISC-V Revolution: How Open Processors Are Changing the CPU Market

RISC-V, an open instruction set architecture (ISA), is reshaping the global computing landscape. Unlike proprietary ISAs such as x86, widely used by Intel and AMD, or ARM, which dominates mobile and ...
ExtremeTech

RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source

A new instruction set by the original creator of MIPS aims to reinvent the ultra-low power, high-efficiency processor -- and to do so with an architecture that's fundamentally open and available to ...
Ars Technica

A history of ARM, part 1: Building the first chip

RISC is a somewhat misleading term, as a RISC processor doesn't *have* to have fewer instructions in its ISA than a CISC system (Though RISC architectures do tend to try to do so). For example, the ...
Semiconductor Engineering

Differentiation And Architecture Licenses In RISC‑V

I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp. In a traditional processor IP ...
Semiconductor Engineering

Dual Instruction-Set Architecture, Supporting A TTA And RISC-V Instruction Set Via a Lightweight Microcode Hardware Unit

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...
Electronic Design

Processor Breaks Architectural Ground

Wireless networking solves many of the cost problems of wired networking by requiring less infrastructure and equipment. Yet wireless networking also must grapple with its own issues. For instance, in ...
EDN

AI is stress-testing processor architectures and RISC-V fits the moment

Every major computing era has been defined not by technology, but by a dominant workload—and by how well processor architectures adapted to it. The personal computer era rewarded general-purpose ...
InfoWorld

IBM’s Power5 processor worth a second look

The Power architecture doesn’t get the attention it deserves. With Power5 servers finally shipping, even non-Big Blue shops should take look again If all things were equal and IBM made its systems as ...