Design-Reuse

Fujitsu and Denali Software Collaborate to Develop DFI Compatible DDR PHY Macro

Hamamatsu City, Shizuoka, Japan -- Sept 19, 2007-- Fujitsu Limited and Denali Software, Inc. today announced their co-development of a DDR DRAM physical interface (DDR PHY) product compatible with the ...
Design-Reuse

Cadence and Denali Team Up to Enable Advanced DDR-PHY Methodology

Industry's Most Advanced DDR-PHY Solutions Achieved With Denali's Databahn PHY Architecture and CPF-Enabled Cadence SoC Encounter and Encounter Timing System SAN JOSE, CA -- May 31, 2007-- Cadence ...
EDN

Design tool yields DDR memory interface IP

The DDR PHY compiler is said to be the industry’s first DDR SDRAM design tool. It enables assembly of a complete, customized high-performance DDR PHY for ASICs, ASSPs, or SoC applications while ...
EDN

Industry Collaboration Marches Ahead with Official Release of DDR PHY Interface Specification Version 2.0 Accelerating DDR Memory System Development

SUNNYVALE, Calif., May 21, 2008 – Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members including ARM, Denali, Intel, and Samsung, announced the ...
Electronic Design

DDR3 and DDR2 Memory IP Bolsters SoC Designs

A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare ...
Business Wire

Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, supporting from 3 rd ...
Electronic Design

Cadence and Denali Double-Team Advanced DDR-PHY Methodology

The combined resources of Cadence Design Systems and Denali Software have resulted in an advanced double-data-rate (DDR) PHY methodology based on Cadence’s Encounter digital IC design platform. The ...