IEEE

FPGA IP Core for DC Motor Control With Adaptive Neural Network PID Tuning, and High-Resolution Encoder Interface

Abstract: Traditional proportional integral derivative (PID) falls short for precise control of DC motor speed under changing conditions. This paper presents a novel FPGA based IP (intellectual ...
IEEE

A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow

Abstract: Object detection models have demonstrated outstanding performance in terms of accuracy. However, mapping convolutional neural network-based object-detection models to memory and ...
BizTech

What Is an FPGA? Understanding Field-Programmable Gate Arrays

Ernie Smith is a former contributor to BizTech, an old-school blogger who specializes in side projects, and a tech history nut who researches vintage operating systems for fun. When it comes to major ...
GitHub

An operating system for FPGAs

The inspiration for Coyote comes from the drastic changes in the hardware landscape of datacenter and cloud computing. With the inevitable end of Moore’s Law and Dennard Scaling, new generations of ...