Abstract: A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR with a ...
Abstract: This paper presents a passive-charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) that achieves 16-bit linearity. It is known that on-chip passive charge ...
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