Abstract: This paper presents a 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-linearity data acquisition modules in precision industrial process ...
Requires Python >= 3.9 and NumPy >= 2.0. For non-byte-aligned widths (e.g. 12-bit), values are zero-padded in the most significant bits to fill whole bytes (2 bytes for 12-bit).
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